The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a built-in capacitor and a manufacturing method thereof.
A so-called microwave monolithic integrated circuit (MMIC) is a semiconductor device designed for use in the ultra-high frequency (UHF) range or in the super-high frequency (SHF) range. Such an integrated circuit for microwave application often uses a shunt capacitor having an electrode connected to the ground.
FIG. 1 shows a typical MMIC device comprising a pair of FETs forming a two-stage amplifier circuit. In this device, a plurality of capacitors C.sub.1 are interposed in a signal path extending from an input terminal IN to an output terminal OUT and there is further provided a shunt capacitor C.sub.2 in the vicinity of a gate biasing terminal G or a drain biasing terminal D for removing unwanted high frequency components. Further, there is another shunt capacitor C.sub.3 connected to the signal path for achieving impedance matching.
Conventionally, impedance matching of the signal path in the MMIC is achieved by providing an open stab acting as a capacitance, of which its size is adjusted so as to achieve proper impedance matching. However, such an open stab occupies a large area and needs trimming to establish a desired impedance. It is preferred to achieve such an impedance matching by using the shunt capacitor C.sub.3 designed to have a proper capacitance value. The present invention is mainly related to such a shunt capacitor having one electrode connected to the ground or other constant voltage source for bypassing the high frequency component to the ground or used for impedance matching.
FIG. 2 is a cross sectional view showing the structure of a prior art shunt capacitor. Referring to the drawing, the shunt capacitor comprises a semi-insulating substrate 11 of gallium arsenide, and an internal electrode 12a is provided on the substrate in correspondence to where the capacitor is to be formed. On the internal electrode 12a, there is further provided a dielectric film 12b and a surface electrode 12c is provided further thereon so as to make an electrical contact with the dielectric film 12b. This surface electrode 12c is connected to a transmission strip 13 forming the signal path. On the rear, or bottom substrate 11, it can be seen that there is formed a large through hole 10 in correspondence to the internal electrode 12a so as to expose a central part of the electrode 12a, and a ground electrode 14 is provided on the bottom of the substrate 11 including an inner surface 10a of the contact hole 10. Further, the ground electrode 14 is connected to a metal base 15 having a ground potential level via a brazing filler 16 and thus there is formed a shunt capacitor region having one electrode 12c connected to the transmission strip 13 and the other electrode 14 connected to the ground. Conventionally, the contact hole 10 is formed by removing a part of the substrate 11 corresponding to the contact hole 10 by isotropic etching. FIG. 3 shows a connection of the shunt capacitor of FIG. 2 to the MMIC shown in FIG. 1. As can be seen in the drawing, the transmission strip 13 formed on the substrate 11 is connected to the surface electrode 12c via an airbridge structure 13a.
In such a prior art capacitor, there is a problem in that the shunt capacitor thus formed is mechanically fragile as the through hole 10 has a semi-circular vertical cross section which contacts tangentially with the internal electrode 12a and there is formed a thin central region in the substrate 11 in correspondence to a central part of the contact hole 10. When the substrate 11 is brazed on the metal base 15, for example, there usually remains a small amount of air at the top of the brazing filler 16 filling the contact hole 10 as designated by a space 15a. The air filling the space 15a reduces its volume upon cooling and as a result, the thin region at the central part of the contact hole 10 tends to be broken because of the air pressure acting on the central part of the contact hole 10.
In the prior art capacitor illustrated in FIG. 1, there exists another problem in that one has to provide an unnecessarily large internal electrode 12a so as to tolerate variation of size of the contact hole 10, as the exact control of wet etching to form the contact hole 10 having an exact size is difficult in the presently available technique. Associated therewith, there are formed a number of parasitic paths between the internal electrode 12a and the bottom electrode 14 as illustrated in FIG. 1 by parasitic capacitors C.sub. -C.sub.3 and as a result, there arises still another problem in that the electrical property of the shunt capacitor is deviated from the designed value. As the region of the substrate 11 corresponding to the central part of the contact hole 10 has a reduced thickness, the effect of these parasitic capacitors is not negligible. Because of the poor control of the size of the contact hole 10 as already described, it is not possible to design the shunt capacitor by taking the effect of these parasitic capacitors into consideration in advance.
Further, as a result of the excessive extension of the internal electrode 12a, a part of the high frequency signal component which has passed the dielectric film 12b from the surface electrode 12c to the internal electrode 12a is guided to the bottom electrode 14 by passing through the internal electrode 12a laterally. Thereby, the high frequency signal component experiences inductance formed by the internal electrode 12a.
FIG. 4 shows an equivalent circuit diagram of the shunt capacitor of FIG. 2. In the drawing, the capacitance of the dielectric film 12b is represented by C.sub.0 and the designed capacitance value C of the shunt capacitor 12 is given by a parallel connection of the capacitors C.sub.0. Further, it can be seen that there appear parasitic inductances L.sub.1 -L.sub.3 extending laterally along the internal electrode 12a and each end of each of the inductances L.sub.1 -L.sub.3 is connected to the ground by the aforementioned parasitic capacitors C.sub.1 -C.sub.3. As a result, there is formed a parasitic circuit C' comprising the parasitic inductances L.sub.1 -L.sub.3 and the parasitic capacitances C.sub.1 -C.sub.3 interposed between the capacitor 12 and the ground electrode 14. Note that the parasitic capacitors C.sub.1 at the central region of the contact hole 10 has a capacitance which cannot be neglected because of the reduced thickness at the central region of the contact hole 10 while the respective capacitances of the capacitors C.sub.2 and C.sub.3 decrease in value towards the marginal region of the contact hole 10 because of the increased thickness of the substrate 11. Further, there is formed an additional parasitic inductance L.sub.0 between the internal electrode 12a and the ground electrode 14 at the center of the contact hole 10. In one example, it was found that the parasitic inductances L.sub.1 -L.sub.3 are about ten times larger than the parasitic inductance L.sub.0. In other words, the effect of the parasitic inductances L.sub.1 -L.sub.3 cannot be neglected. Thus, the impedance of the parasitic circuit C' in FIG. 3 is not negligible. To make the matter worse, the impedance of the parasitic circuit C' is varied device by device.